Modern digital electronic circuits use clock signals to time inputs and outputs. As modern integrated circuit manufacturing technology has advanced, circuits are able to operate at faster and faster speeds. For example, modern complementary metal-oxide-semiconductor (CMOS) technology allows logic circuits that can operate using clock speeds well above 1 gigahertz (GHz).
The higher-speed operation supported by modern integrated circuit technology has created certain problems. For example, when two or more integrated circuits provide output signals representing different slices of the same processed input signal, such as analog-to-digital (A/D) converters and the like, it is necessary that the output signals be synchronized to each other so that another circuit, such as a microprocessor or application-specific integrated circuit (ASIC), can process the multiple outputs as a unit. In order to solve these problems, the Joint Electron Devices Engineering Council (JEDEC) has promulgated a standard for synchronizing outputs across multiple integrated circuits for data converters in standard JESD204b/c. This standard specifies a system-level frame synchronization command, known as “˜SYNC”. Other systems use other similar techniques and signaling, such as a “SYNC” input signal, to synchronize outputs between different integrated circuits.
In these systems, each integrated circuit operates asynchronously to the system clock and to SYNC, and must internally capture the state of the SYNC signal to synchronize the output of a frame of data. In some circumstances, however, the SYNC signal can transition about the same time as an internally generated clock signal that is used to time the output signals. In this case, an internal circuit that samples the SYNC signal may become metastable.
For example, a capturing circuit such as a flip-flop may be unable to capture the external SYNC signal when it changes at about the same time as a transition in the internal clock signal. Not only is the data not “caught” or captured correctly at that edge, but additionally the capturing circuit suffers from a “confusion” of sorts. It captures a “confused” or intermediate mid-point value which is then output to the next stage requiring data. The time it takes for the capturing circuit to become “unconfused” can be statistically determined, but can be in some rare cases quite long. The bigger problem is not that the data is not captured perfectly at the exact earliest edge possible, but that the capturing device can be forced into this confused state. The confused state is known as metastability.
There are known circuits that detect metastability and keep their outputs in a certain state, such as a low state, until the metastability passes. However even these metastability-free circuits have an indeterminate time before the output signal transitions, which creates what is known as timing ambiguity. The delayed transition adds to output/output delay between the integrated circuits, which can prevent the system from meeting timing specifications.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.